EP4CE30F29C7N Datasheet, PDF (283/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

Chapter 1: Cyclone IV Transceivers Architecture
1–3
Transceiver Architecture
Figure 1–2. F484 and Larger Packages with Transceiver Channels for Cyclone IV GX Devices
MPLL_8 GPLL_2
Transceiver
Block GXBL1
Channel 3
Channel 2
Channel 1
Channel 0
Not applicable in
F484 package
MPLL_7
F484 and larger
packages
MPLL_6
Transceiver
Block GXBL0
Channel 3
Channel 2
Channel 1
Channel 0
Calibration Block
MPLL_5 GPLL_1
PCIe
hard IP
For more information about the transceiver architecture, refer to the following
sections:
■ “Architectural Overview” on page 1–4
■ “Transmitter Channel Datapath” on page 1–5
■ “Receiver Channel Datapath” on page 1–11
■ “Transceiver Clocking Architecture” on page 1–26
■ “Transceiver Channel Datapath Clocking” on page 1–29
■ “FPGA Fabric-Transceiver Interface Clocking” on page 1–43
■ “Calibration Block” on page 1–45
■ “PCI-Express Hard IP Block” on page 1–46
October 2013 Altera Corporation
Cyclone IV Device Handbook,
Volume 2