EP4CE30F29C7N Datasheet, PDF (198/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

8–34
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
To ensure DCLK and DATA[0] are not left floating at the end of configuration, the
MAX II device must drive them either high or low, whichever is convenient on your
board. The DATA[0] pin is available as a user I/O pin after configuration. In the PS
scheme, the DATA[0] pin is tri-stated by default in user mode and must be driven by
the external host device. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device and Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified system frequency to
ensure correct configuration. No maximum DCLK period exists, which means you can
pause configuration by halting DCLK for an indefinite amount of time.
The external host device can also monitor CONF_DONE and INIT_DONE to ensure
successful configuration. The CONF_DONE pin must be monitored by the external device
to detect errors and to determine when programming is complete. If all configuration
data is sent, but CONF_DONE or INIT_DONE has not gone high, the external device must
reconfigure the target device.
Figure 8–14 shows how to configure multiple devices using an external host device.
This circuit is similar to the PS configuration circuit for a single device, except that
Cyclone IV devices are cascaded for multi-device configuration.
Figure 8–14. Multi-Device PS Configuration Using an External Host
Memory
V_{CCIO (1)} V_{CCIO (1)}
ADDR DATA[0]
10 k 10 k
External Host
(MAX II Device or
Microprocessor)
GND
Cyclone IV Device 1
(4)
MSEL[ ]
CONF_DONE
nSTATUS
nCE
nCEO
DATA[0] (5)
nCONFIG
DCLK (5)
V_{CCIO (2)}
Cyclone IV Device 2
10 k
MSEL[ ]
(4)
CONF_DONE
nSTATUS
nCE
nCEO
N.C. (3)
DATA[0] (5)
nCONFIG
DCLK (5)
Buffers (5)
Notes to Figure 8–14:
(1) The pull-up resistor must be connected to a supply that provides an acceptable input signal for all devices in the
chain. V_CC must be high enough to meet the V_IH specification of the I/O on the device and the external host.
(2) Connect the pull-up resistor to the V_CCIO supply voltage of the I/O bank in which the nCE pin resides.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
refer to Table 8–3 on page 8–8, Table 8–4 on page 8–8, and Table 8–5 on page 8–9. Connect the MSEL pins directly
to V_CCA or GND.
(5) All I/O inputs must maintain a maximum AC voltage of 4.1 V. DATA[0] and DCLK must fit the maximum overshoot
outlined in Equation 8–1 on page 8–5.
Cyclone IV Device Handbook,
Volume 1
May 2013 Altera Corporation