EP4CE30F29C7N Datasheet, PDF (54/488 Pages) Altera Corporation – Cyclone IV Device Handbook, Volume 1

3–18
Chapter 3: Memory Blocks in Cyclone IV Devices
Document Revision History
Power-Up Conditions and Memory Initialization
The M9K memory block outputs of Cyclone IV devices power up to zero (cleared)
regardless of whether the output registers are used or bypassed. All M9K memory
blocks support initialization using a .mif. You can create .mifs in the Quartus II
software and specify their use using the RAM MegaWizard Plug-In Manager when
instantiating memory in your design. Even if memory is pre-initialized (for example,
using a .mif), it still powers up with its outputs cleared. Only the subsequent read
after power up outputs the pre-initialized values.
f For more information about .mifs, refer to the RAM Megafunction User Guide and the
Quartus II Handbook.
Power Management
The M9K memory block clock enables of Cyclone IV devices allow you to control
clocking of each M9K memory block to reduce AC power consumption. Use the rden
signal to ensure that read operations only occur when necessary. If your design does
not require read-during-write, reduce power consumption by deasserting the rden
signal during write operations or any period when there are no memory operations.
The Quartus II software automatically powers down any unused M9K memory
blocks to save static power.
Document Revision History
Table 3–6 shows the revision history for this chapter.
Table 3–6. Document Revision History
Date
November 2011
November 2009
Version
1.1
1.0
Changes
Updated the “Byte Enable Support” section.
Initial release.
Cyclone IV Device Handbook,
Volume 1
November 2011 Altera Corporation