SH7606 Datasheet, PDF (99/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Table 5.8 Interrupt Priority
Type
NMI
User break
H-UDI
IRQ
On-chip peripheral module
Priority Level
16
15
15
0 to 15
Section 5 Exception Handling
Comment
Fixed priority level. Cannot be masked.
Fixed priority level. Can be masked.
Fixed priority level.
Set with interrupt priority level setting registers
A through E (IPRA to IPRE).
5.4.3 Interrupt Exception Handling
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception handling begins. In interrupt exception handling, the
CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted
interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set
in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched
from the exception handling vector table for the accepted interrupt, and program execution
branches to that address and the program starts. For details on the interrupt exception handling, see
section 6.6, Interrupt Operation.
Rev. 4.00 Sep. 13, 2007 Page 73 of 502
REJ09B0239-0400