SH7606 Datasheet, PDF (246/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 10 Power-Down Modes
10.4 Sleep Mode
10.4.1 Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip peripheral
modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.
10.4.2 Canceling Sleep Mode
Sleep mode is canceled by an interrupt other than a user break (NMI, H-UDI, IRQ, and on-chip
peripheral module) or a reset.
Canceling with Interrupt: When a user-break, NMI, H-UDI, IRQ, or on-chip peripheral module
interrupt occurs, sleep mode is canceled and interrupt exception handling is executed. When the
priority level of an IRQ or on-chip peripheral module interrupt is lower than the interrupt mask
level set in the status register (SR) of the CPU, an interrupt request is not accepted preventing
sleep mode from being canceled.
Canceling with Reset: Sleep mode is canceled by a power-on reset or an H-UDI reset.
10.5 Software Standby Mode
10.5.1 Transition to Software Standby Mode
This LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the
CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin
also halts.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. Table 10.3 lists the states of on-chip peripheral
modules registers in software standby mode.
Rev. 4.00 Sep. 13, 2007 Page 220 of 502
REJ09B0239-0400