SH7606 Datasheet, PDF (289/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode)
Pφ (MHz)
5
4.9152
8
9.8304
12
14.7456
16
19.6608
20
24
24.576
28.7
30
33
External Input Clock (MHz)
1.2500
1.2288
2.0000
2.4576
3.0000
3.6864
4.0000
4.9152
5.0000
6.0000
6.1440
7.1750
7.5000
8.25
Maximum Bit Rate (bits/s)
78125
76800
125000
153600
187500
230400
250000
307200
312500
375000
384000
448436
468750
515625
Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)
Pφ (MHz)
5
8
16
24
28.7
30
33
External Input Clock (MHz)
0.8333
1.3333
2.6667
4.0000
4.7833
5.0000
5.5000
Maximum Bit Rate (bits/s)
833333.3
1333333.3
2666666.7
4000000.0
4783333.3
5000000.0
5500000.0
12.3.9 FIFO Control Register (SCFCR)
SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO
registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.
Rev. 4.00 Sep. 13, 2007 Page 263 of 502
REJ09B0239-0400