SH7606 Datasheet, PDF (252/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 11 Compare Match Timer (CMT)
11.2 Register Descriptions
The CMT has the following registers.
• Compare match timer start register (CMSTR)
• Compare match timer control/status register_0 (CMCSR_0)
• Compare match counter_0 (CMCNT_0)
• Compare match constant register_0 (CMCOR_0)
• Compare match timer start register_1 (CMSTR_1)
• Compare match timer control/status register_1 (CMCSR_1)
• Compare match counter_1 (CMCNT_1)
• Compare match constant register_1 (CMCOR_1)
11.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
CMSTR is initialized to H'0000 by a power-on reset and a transition to standby mode.
Bit
15 to 2
Bit Name

1
STR1
0
STR0
Initial
value
All 0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start 1
Specifies whether compare match counter 1 operates
or is stopped.
0: CMCNT_1 count is stopped
1: CMCNT_1 count is started
R/W Count Start 0
Specifies whether compare match counter 0 operates
or is stopped.
0: CMCNT_0 count is stopped
1: CMCNT_0 count is started
Rev. 4.00 Sep. 13, 2007 Page 226 of 502
REJ09B0239-0400