SH7606 Datasheet, PDF (140/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
7.3.4 Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, the bus width is selected
from 8 bits and 16 bits at a power-on reset by the external pin setting. The bus width of other areas
is set by the register. The correspondence between the memory type, external pin (MD3), and bus
width is listed in table 7.4.
Table 7.4 Correspondence between External Pin (MD3), Memory Type, and Bus Width
for CS0
MD3
1
0
Memory Type
Normal memory
Bus Width
8 bits
16 bits
7.3.5 Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at a power-on reset as shown in table 7.5.
Table 7.5 Correspondence between External Pin (MD5) and Endians
MD5
0
1
Endian
Big endian
Little endian
Rev. 4.00 Sep. 13, 2007 Page 114 of 502
REJ09B0239-0400