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SH7606 Datasheet, PDF (131/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series | |||
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Section 6 Interrupt Controller (INTC)
Table 6.3 Interrupt Response Time
Number of Cycles
Item
NMI, H-UDI
IRQ, Peripheral
Modules
Remarks
Interrupt priority decision
and comparison with mask
bits in SR
1 Ã Icyc + 2 Ã Pcyc 1 Ã Icyc + 3 Ã Pcyc
Wait for completion of
sequence currently being
executed by CPU
X (⥠0)
X (⥠0)
The longest sequence
is for interrupt or
address-error
exception handling (X =
7 Ã Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
8 Ã Icyc + m1 + m2 8 Ã Icyc + m1 + m2
+ m3
+ m3
Performs the saving
PC and SR, and vector
address fetch.
Interrupt
response
time
Total: 9 Ã Icyc + 2 Ã Pcyc 9 Ã Icyc + 3 Ã Pcyc
+ m1 + m2 + m3 + m1 + m2 + m3
+X
+X
Minimum*: 12 Ã Icyc +
2 Ã Pcyc
12 Ã Icyc +
3 Ã Pcyc
SR, PC, and vector
table are all in on-chip
RAM, or cache hit
occurs (in write back
mode).
Maximum:
16 Ã Icyc +
2 Ã Pcyc + 2 Ã
(m1 + m2 + m3) +
m4
16 Ã Icyc +
3 Ã Pcyc + 2 Ã
(m1 + m2 + m3) +
m4
Notes: *
In the case that m1 = m2 = m3 = m4 = 1 Ã Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev. 4.00 Sep. 13, 2007 Page 105 of 502
REJ09B0239-0400
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