SH7606 Datasheet, PDF (187/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Table 7.14 Relationship between Register Settings and Address Multiplex Output (5)
Conditions: One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 9-bit column product) is
connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 10 (13-bit
row address), and A3COL[1:0] = 01 (9-bit column address).
Output Row
Pins of this LSI Address
Output Column
Address
Pins of SDRAM Function
A17
A26
A17
Unused
A16
A25
A16
A15
A24*²
A24*²
A14 (BA1)
Specifies bank
A14
A23*²
A23*²
A13 (BA0)
A13
A22
A13
A12
Address
A12
A21
A12
A11
A11
A20
L/H*¹
A10/AP
Specifies
address/precharge
A10
A19
A10
A9
Address
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Rev. 4.00 Sep. 13, 2007 Page 161 of 502
REJ09B0239-0400