SH7606 Datasheet, PDF (262/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Four types of interrupts: Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and
receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous, on-chip modem control functions (RTS and CTS) (only for channel 1 and
channel 0).
• The number of data in the transmit and receive FIFO registers and the number of receive errors
of the receive data in the receive FIFO register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
Figure 12.1 shows a block diagram of the SCIF for each channel.
Rev. 4.00 Sep. 13, 2007 Page 236 of 502
REJ09B0239-0400