SH7606 Datasheet, PDF (247/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 10 Power-Down Modes
Table 10.3 Register States in Software Standby Mode
Module
Interrupt controller (INTC)
Clock pulse generator (CPG)
User break controller (UBC)
Bus state controller (BSC)
I/O port
User debugging interface (H-UDI)
Serial communication interface with FIFO
(SCIF0 to SCIF2)
Compare match timer (CMT0 and CMT1)
Host interface (HIF)
Registers Initialized







All registers

Registers Retaining Data
All registers
All registers
All registers
All registers
All registers
All registers
All registers

All registers
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. Set the timer counter (WTCNT) of the WDT to 0 and bits CKS2 to CKS0 in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. After setting the STBY bit in STBCR to 1, execute the SLEEP instruction.
4. Software standby mode is entered and the clocks within this LSI are halted.
Rev. 4.00 Sep. 13, 2007 Page 221 of 502
REJ09B0239-0400