SH7606 Datasheet, PDF (526/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

SCFSR_1 ............................ 417, 424, 434
SCFSR_2 ............................ 418, 425, 435
SCFTDR............................................. 241
SCFTDR_0 ......................... 417, 424, 434
SCFTDR_1 ......................... 417, 424, 434
SCFTDR_2 ......................... 418, 425, 435
SCLSR................................................ 272
SCLSR_0............................ 417, 424, 434
SCLSR_1............................ 418, 425, 435
SCLSR_2............................ 418, 425, 435
SCRSR................................................ 240
SCSCR................................................ 245
SCSCR_0............................ 417, 424, 434
SCSCR_1............................ 417, 424, 434
SCSCR_2............................ 418, 425, 435
SCSMR............................................... 241
SCSMR_0........................... 417, 423, 434
SCSMR_1........................... 417, 424, 434
SCSMR_2........................... 418, 425, 435
SCSPTR.............................................. 268
SCSPTR_0.......................... 417, 424, 434
SCSPTR_1.......................... 418, 424, 435
SCSPTR_2.......................... 418, 425, 435
SCTSR................................................ 240
SDBPR ............................................... 402
SDBSR ............................................... 403
SDCR...........................138, 419, 429, 436
SDID............................409, 417, 423, 434
SDIR............................402, 417, 423, 434
STBCR ........................216, 417, 423, 434
STBCR2 ......................217, 417, 423, 434
STBCR3 ......................218, 416, 423, 433
STBCR4 ......................219, 416, 423, 433
WTCNT.......................206, 417, 423, 434
WTCSR .......................207, 417, 423, 434
Register data format.................................. 24
Relationship between refresh
requests and bus cycles........................... 178
Reset ......................................................... 69
RISC-type................................................. 25
Rev. 4.00 Sep. 13, 2007 Page 500 of 502
REJ09B0239-0400
S
SCIF Initialization
(Asynchronous Mode) ............................ 277
SCIF initialization
(synchronous mode)................................ 287
SDRAM direct connection...................... 155
SDRAM interface ................................... 155
Searching cache ........................................ 55
Self-refreshing ........................................ 177
Serial communication interface
with FIFO (SCIF).................................... 235
Shift instructions ....................................... 44
Single read .............................................. 166
Single Write ............................................ 168
Sleep mode.............................................. 220
Software standby mode........................... 220
Stack states after exception
handling ends ............................................ 77
State transition .......................................... 48
Synchronous mode.................................. 286
System control instructions....................... 46
System registers ........................................ 23
T
TAP controller ........................................ 410
Transmitting and receiving serial data
simultaneously (synchronous mode)....... 293
Transmitting serial data
(asynchronous mode) .............................. 279
Transmitting serial data
(synchronous mode)................................ 289
Trap instructions ....................................... 74
Types of exception handling
and priority................................................ 65
Types of exceptions triggered by
instructions................................................ 74
Types of power-down modes.................. 213