SH7606 Datasheet, PDF (438/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 17 User Debugging Interface (H-UDI)
TCK
TDO
(when the H-UDI
command is set)
TDO
(when the JTAG
command is set)
t_TDO
t_TDO
Figure 17.3 H-UDI Data Transfer Timing
17.4.4 H-UDI Reset
An H-UDI reset is generated by setting the H-UDI reset assert command in SDIR. An H-UDI reset
is of the same kind as a power-on reset. An H-UDI reset is released by inputting the H-UDI reset
negate command. The required time between the H-UDI reset assert command and H-UDI reset
negate command is the same as time for keeping the RESETP pin low to apply a power-on reset.
SDIR
H-UDI reset assert
H-UDI reset negate
LSI internal reset
CPU state
Branch to H'A0000000
Figure 17.4 H-UDI Reset
17.4.5 H-UDI Interrupt
The H-UDI interrupt function generates an interrupt by setting an H-UDI command in SDIR. An
H-UDI interrupt is an interrupt of general exceptions, resulting in a branch to an address based on
the VBR value plus offset, and with return by the RTE instruction. This interrupt request has a
fixed priority level of 15.
H-UDI interrupts are accepted in sleep mode, but not in standby mode.
Rev. 4.00 Sep. 13, 2007 Page 412 of 502
REJ09B0239-0400