SH7606 Datasheet, PDF (20/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Figure 13.8 HIFDREQ Timing (When DMD = 0 and DPOL = 0)............................................. 323
Figure 13.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)............................................. 324
Figure 13.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0) ........................................... 324
Figure 13.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1) ........................................... 324
Figure 13.12 Image of High-Impedance Control of HIF Pins by HIFEBL Pin .......................... 329
Section 15 I/O Ports
Figure 15.1 Port A ...................................................................................................................... 363
Figure 15.2 Port B ...................................................................................................................... 365
Figure 15.3 Port C ...................................................................................................................... 367
Figure 15.4 Port D ...................................................................................................................... 370
Figure 15.5 Port E....................................................................................................................... 372
Section 16 User Break Controller (UBC)
Figure 16.1 Block Diagram of UBC........................................................................................... 378
Section 17 User Debugging Interface (H-UDI)
Figure 17.1 Block Diagram of H-UDI........................................................................................ 400
Figure 17.2 TAP Controller State Transitions ............................................................................ 410
Figure 17.3 H-UDI Data Transfer Timing.................................................................................. 412
Figure 17.4 H-UDI Reset............................................................................................................ 412
Section 19 Electrical Characteristics
Figure 19.1 External Clock Input Timing................................................................................... 446
Figure 19.2 CKIO Clock Output Timings .................................................................................. 446
Figure 19.3 Oscillation Settling Timing after Power-On............................................................ 446
Figure 19.4 Oscillation Settling Timing after Standby Mode (By Reset)................................... 447
Figure 19.5 Oscillation Settling Timing after Standby Mode (By NMI or IRQ)........................ 447
Figure 19.6 PLL Synchronize Settling Timing by Reset or NMI ............................................... 447
Figure 19.7 Reset Input Timing.................................................................................................. 448
Figure 19.8 Interrupt Input Timing............................................................................................. 449
Figure 19.9 Pin Drive Timing in Standby Mode ........................................................................ 449
Figure 19.10 Basic Bus Timing: No Wait Cycle ........................................................................ 452
Figure 19.11 Basic Bus Timing: One Software Wait Cycle ....................................................... 453
Figure 19.12 Basic Bus Timing: One External Wait Cycle........................................................ 454
Figure 19.13 Basic Bus Timing: One Software Wait Cycle, External Wait Enabled
(WM Bit = 0), No Idle Cycle ................................................................................ 455
Figure 19.14 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle,
One Asynchronous External Wait Cycle, CSnWCR.BAS = 0
(UB-/LB-Controlled Write Cycle) ........................................................................ 456
Rev. 4.00 Sep. 13, 2007 Page xx of xxvi