SH7606 Datasheet, PDF (8/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Contents
Section 1 Overview ............................................................................................... 1
1.1 Features.................................................................................................................................. 1
1.2 Block Diagram....................................................................................................................... 5
1.3 Pin Assignments .................................................................................................................... 6
1.4 Pin Functions ......................................................................................................................... 7
Section 2 CPU ..................................................................................................... 19
2.1 Features................................................................................................................................ 19
2.2 Register Configuration......................................................................................................... 19
2.2.1 General Registers (Rn)............................................................................................ 21
2.2.2 Control Registers .................................................................................................... 21
2.2.3 System Registers..................................................................................................... 23
2.2.4 Initial Values of Registers....................................................................................... 23
2.3 Data Formats........................................................................................................................ 24
2.3.1 Register Data Format .............................................................................................. 24
2.3.2 Memory Data Formats ............................................................................................ 24
2.3.3 Immediate Data Formats......................................................................................... 25
2.4 Features of Instructions........................................................................................................ 25
2.4.1 RISC Type .............................................................................................................. 25
2.4.2 Addressing Modes .................................................................................................. 28
2.4.3 Instruction Formats ................................................................................................. 31
2.5 Instruction Set ...................................................................................................................... 35
2.5.1 Instruction Set by Type........................................................................................... 35
2.6 Processing States.................................................................................................................. 48
2.6.1 State Transition....................................................................................................... 48
Section 3 Cache ................................................................................................... 51
3.1 Features................................................................................................................................ 51
3.1.1 Cache Structure....................................................................................................... 51
3.1.2 Divided Areas and Cache ....................................................................................... 53
3.2 Register Descriptions........................................................................................................... 54
3.2.1 Cache Control Register 1 (CCR1) .......................................................................... 54
3.2.2 Cache Control Register 3 (CCR3) .......................................................................... 55
3.3 Operation ............................................................................................................................. 55
3.3.1 Searching Cache ..................................................................................................... 55
3.3.2 Read Access............................................................................................................ 56
Rev. 4.00 Sep. 13, 2007 Page viii of xxvi