SH7606 Datasheet, PDF (54/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 2 CPU
Table 2.7 Access with Displacement
Type
CPU in this LSI
16-bit displacement MOV.W @(disp,PC),R0
MOV.W @(R0,R1),R2
........
.DATA.W H'1234
Note: * Immediate data is referenced by @(disp,PC).
Example of Other CPUs
MOV.W
@(H'1234,R1),
R2
2.4.2 Addressing Modes
Table 2.8 lists addressing modes and effective address calculation methods.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format Effective Address Calculation Method
Register
Rn
direct
Effective address is register Rn.
(Operand is register Rn contents.)
Register
indirect
@Rn
Effective address is register Rn contents.
Rn
Rn
Register
@Rn+
indirect with
post-increment
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn + 1/2/4
+
1/2/4
Calculation
Formula

Rn
Rn
After instruction
execution
Byte: Rn + 1 →
Rn
Word: Rn + 2 →
Rn
Longword: Rn + 4
→ Rn
Rev. 4.00 Sep. 13, 2007 Page 28 of 502
REJ09B0239-0400