SH7606 Datasheet, PDF (350/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
DTRG bit
DPOL bit
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
HIFDREQ
HIFCS
HIFRS
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
Negated when HIFCS = HIFRS = low level.
Latency is tPCYC (peripheral clock cycle) × 3 cyc or less.
Figure 13.9 HIFDREQ Timing (When DMD = 0 and DPOL = 1)
When the external DMAC is specified to detect the falling edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 0. After writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is
generated at the HIFDREQ pin.
DTRG bit
DPOL bit
HIFDREQ
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
After assert, negated when
tPCYC (peripheral clock cycle) × 32 cyc have elapsed.
Figure 13.10 HIFDREQ Timing (When DMD = 1 and DPOL = 0)
When the external DMAC is specified to detect the rising edge of the HIFDREQ signal, set DMD
= 1 and DPOL = 1. At the time the DPOL bit is set to 1, HIFDREQ becomes low. Then after
writing 1 to the DTRG bit, a low pulse of 32 peripheral clock cycles is generated at the HIFDREQ
pin.
DTRG bit
DPOL bit
Negated in synchronization
with the DPOL bit being set
by the on-chip CPU.
HIFDREQ
Asserted in synchronization
with the DTRG bit being set
by the on-chip CPU.
The DTRG bit is cleared
simultaneously with
HIFDREQ negate.
After assert, negated when
tPCYC (peripheral clock cycle) × 32 cyc have elapsed.
Figure 13.11 HIFDREQ Timing (When DMD = 1 and DPOL = 1)
Rev. 4.00 Sep. 13, 2007 Page 324 of 502
REJ09B0239-0400