SH7606 Datasheet, PDF (19/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Figure 11.3 Count Timing .......................................................................................................... 229
Figure 11.4 Timing of CMF Setting ........................................................................................... 230
Figure 11.5 Conflict between Write and Compare-Match Processes of CMCNT ...................... 231
Figure 11.6 Conflict between Word-Write and Count-Up Processes of CMCNT...................... 232
Figure 11.7 Conflict between Byte-Write and Count-Up Processes of CMCNT ....................... 233
Section 12 Serial Communication Interface with FIFO (SCIF)
Figure 12.1 Block Diagram of SCIF........................................................................................... 237
Figure 12.2 Example of Data Format in Asynchronous Communication
(8-Bit Data with Parity and Two Stop Bits) ............................................................ 275
Figure 12.3 Sample Flowchart for SCIF Initialization ............................................................... 278
Figure 12.4 Sample Flowchart for Transmitting Serial Data ...................................................... 279
Figure 12.5 Example of Transmit Operation (8-Bit Data, Parity, One Stop Bit)........................ 281
Figure 12.6 Example of Operation Using Modem Control (CTS).............................................. 281
Figure 12.7 Sample Flowchart for Receiving Serial Data .......................................................... 282
Figure 12.8 Sample Flowchart for Receiving Serial Data (cont)................................................ 283
Figure 12.9 Example of SCIF Receive Operation (8-Bit Data, Parity, One Stop Bit)................ 285
Figure 12.10 Example of Operation Using Modem Control (RTS)............................................ 285
Figure 12.11 Data Format in Synchronous Communication ...................................................... 286
Figure 12.12 Sample Flowchart for SCIF Initialization.............................................................. 288
Figure 12.13 Sample Flowchart for Transmitting Serial Data .................................................... 289
Figure 12.14 Example of SCIF Transmit Operation................................................................... 290
Figure 12.15 Sample Flowchart for Receiving Serial Data (1)................................................... 291
Figure 12.16 Sample Flowchart for Receiving Serial Data (2)................................................... 291
Figure 12.17 Example of SCIF Receive Operation .................................................................... 292
Figure 12.18 Sample Flowchart for Transmitting/Receiving Serial Data................................... 293
Figure 12.19 RTSIO Bit, RTSDT Bit, and RTS Pin................................................................... 295
Figure 12.20 CTSIO Bit, CTSDT Bit, and CTS Pin................................................................... 296
Figure 12.21 SCKIO Bit, SCKDT Bit, and SCK Pin ................................................................. 297
Figure 12.22 SPBIO Bit, SPBDT Bit, and TxD Pin ................................................................... 297
Figure 12.23 SPBDT Bit and RxD Pin ....................................................................................... 298
Figure 12.24 Receive Data Sampling Timing in Asynchronous Mode ...................................... 299
Section 13 Host Interface (HIF)
Figure 13.1 Block Diagram of HIF............................................................................................. 302
Figure 13.2 HIF Connection Example ........................................................................................ 304
Figure 13.3 Basic Timing for HIF Interface ............................................................................... 320
Figure 13.4 HIFIDX Write and HIFGSR Read .......................................................................... 321
Figure 13.5 HIF Register Settings .............................................................................................. 321
Figure 13.6 Consecutive Data Writing to HIFRAM................................................................... 322
Figure 13.7 Consecutive Data Reading from HIFRAM ............................................................. 322
Rev. 4.00 Sep. 13, 2007 Page xix of xxvi