SH7606 Datasheet, PDF (120/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 6 Interrupt Controller (INTC)
6.3.4 Interrupt Priority Registers A to E (IPRA to IPRE)
Interrupt priority registers are five 16-bit readable/writable registers that set priority levels from 0
to 15 for interrupts except NMI. For the correspondence between interrupt request sources and
IPR, refer to table 6.2. Each of the corresponding interrupt priority ranks are established by setting
a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved
bits that are not assigned should be set H'0 (B'0000).
Initial
Bit
Bit Name Value R/W Description
15
IPR15
0
14
IPR14
0
13
IPR13
0
12
IPR12
0
R/W Set priority levels for the corresponding interrupt
R/W ^source.
R/W ^{0000: Priority level 0 (lowest)}
R/W ^{0001: Priority level 1}
0010: Priority level 2
0011: Priority level 3
0100: Priority level 4
0101: Priority level 5
0110: Priority level 6
0111: Priority level 7
1000: Priority level 8
1001: Priority level 9
1010: Priority level 10
1011: Priority level 11
1100: Priority level 12
1101: Priority level 13
1110: Priority level 14
1111: Priority level 15 (highest)
Rev. 4.00 Sep. 13, 2007 Page 94 of 502
REJ09B0239-0400