SH7606 Datasheet, PDF (269/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 12 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
4
O/E
0
R/W Parity Mode
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only in
asynchronous mode and only when the parity enable
bit (PE) is set to 1 to enable parity addition and
checking. The O/E setting is ignored in synchronous
mode, or in asynchronous mode when parity addition
and checking is disabled.
0: Even parity*¹
1: Odd parity*²
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character and
parity bit combined. Receive data is checked
to see if it has an even number of 1s in the
received character and parity bit combined.
2. If odd parity is selected, the parity bit is
added to transmit data to make an odd
number of 1s in the transmitted character and
parity bit combined. Receive data is checked
to see if it has an odd number of 1s in the
received character and parity bit combined.
Rev. 4.00 Sep. 13, 2007 Page 243 of 502
REJ09B0239-0400