SH7606 Datasheet, PDF (346/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
13.6 Interface (Basic)
Figure 13.3 shows the basic read/write sequence. HIF read is defined by the overlap period of the
HIFRD low-level period and HIFCS low-level period, and HIF write is defined by the overlap
period of the HIFWR low-level period and HIFCS low-level period. The HIFRS signal indicates
whether this is normal access or index/status register access; low level indicates normal access and
high level indicates index/status register access.
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
Write cycle
Read cycle
WT_D
RD_D
Figure 13.3 Basic Timing for HIF Interface
Rev. 4.00 Sep. 13, 2007 Page 320 of 502
REJ09B0239-0400