SH7606 Datasheet, PDF (428/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 17 User Debugging Interface (H-UDI)
17.3 Register Descriptions
The H-UDI has the following registers. For details on the addresses of these registers and the
states of these registers in each processing state, see section 18, List of Registers.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary scan register (SDBSR)
• ID register (SDID)
17.3.1 Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass
mode, SDBPR is connected between H-UDI pins (TDI and TDO). The initial value is undefined.
17.3.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register. This register is in JTAG IDCODE in its initial state. It is
initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-
UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in
this register.
Bit
15 to 13
12
11 to 8
Bit Name
TI7 to TI5
TI4
TI3 to TI0
7 to 2 
1

0

Initial
Value R/W
All 1 R
0
R
All 1 R
All 1 R
0
R
1
R
Description
Test Instruction 7 to 0
The H-UDI instruction is transferred to SDIR by a serial
input from TDI.
For commands, see table 17.2.
Reserved
These bits are always read as 1.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.
Rev. 4.00 Sep. 13, 2007 Page 402 of 502
REJ09B0239-0400