SH7606 Datasheet, PDF (234/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 9 Watchdog Timer (WDT)
Initial
Bit
Bit Name Value R/W
7
TME
0
R/W
6
WT/IT 0
R/W
5

0
R
4
WOVF 0
R/W
3
IOVF
0
R/W
Description
Timer Enable
Starts and stops timer operation. Clear this bit to 0
when using the WDT in software standby mode or
when changing the clock frequency.
0: Timer disabled: Count-up stops and WTCNT value
is retained
1: Timer enabled
Timer Mode Select
Selects whether to use the WDT as a watchdog timer
or an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Note: If WT/IT is modified when the WDT is
operating, the up-count may not be performed
correctly.
Reserved
This bit is always red as 0. The write value should
always be 0.
Watchdog Timer Overflow
Indicates that WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
Interval Timer Overflow
Indicates that WTCNT has overflowed in interval timer
mode. This bit is not set in watchdog timer mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
Rev. 4.00 Sep. 13, 2007 Page 208 of 502
REJ09B0239-0400