SH7606 Datasheet, PDF (416/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 16 User Break Controller (UBC)
16.3 Operation
16.3.1 Flow of User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses are set in the break address registers (BARA and BARB). The masked
addresses are set in the break address mask registers (BAMRA and BAMRB). The break data
is set in the break data register (BDRB). The masked data is set in the break data mask register
(BDMRB). The bus break conditions are set in the break bus cycle registers (BBRA and
BBRB). There are three control bit combinations in both BBRA and BBRB: bits to select L-
bus cycle or I-bus cycle, bits to select instruction fetch or data access, and bits to select read or
write. No user break will be generated if one of these combinations is set to B'00. The
respective conditions are set in the bits of the break control register (BRCR). Make sure to set
all registers related to breaks before setting BBRA/BBRB.
2. When the break conditions are satisfied, the UBC sends a user break request to the CPU and
sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition match
flag (SCMFDA or SCMFDB) for the appropriate channel.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags.
Reset the flags by writing 0 before they are used again.
4. There is a chance that the data access break and its following instruction fetch break occur
around the same time, there will be only one break request to the CPU, but these two break
channel match flags could be both set.
Rev. 4.00 Sep. 13, 2007 Page 390 of 502
REJ09B0239-0400