SH7606 Datasheet, PDF (222/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 8 Clock Pulse Generator (CPG)
8.2 Input/Output Pins
Table 8.1 shows the CPG pin configuration.
Table 8.1 Pin Configuration
Pin Name
Abbr. I/O
Description
Mode control pins* MD0
Input
Set the clock operating mode.
MD1
Input
Set the clock operating mode.
MD2
Input
Set the clock operating mode.
Clock input pins XTAL Output
Connects a crystal resonator.
EXTAL Input
Connects a crystal resonator or an external clock.
Clock output pin CKIO Output
Outputs an external clock.
Note: * The values of these mode control pins are sampled only at a power-on reset or in a
software standby with the MDCHG bit in STBCR to 1. This can prevent the erroneous
operation of this LSI.
8.3 Clock Operating Modes
Table 8.2 shows the relationship between the mode control pins (MD2 to MD0) combinations and
the clock operating modes. Table 8.3 shows the usable frequency ranges in the clock operating
modes and the frequency range of the input clock.
Table 8.2 Mode Control Pins and Clock Operating Modes
Clock
Pin Values
Operating
Mode
MD2 MD1 MD0
1
001
2
010
Clock I/O
Source
Output
EXTAL
CKIO
Crystal resonator CKIO
5
101
EXTAL
CKIO
6
110
Crystal resonator CKIO
PLL2
ON (×4)
ON (×4)
ON (×2)
ON (×2)
PLL1
CKIO Frequency
ON (×1, ×2) (EXTAL) × 4
ON (×1, ×2) (Crystal resonator) ×
4
ON (×1, ×2) (EXTAL) × 2
ON (×1, ×2) (Crystal resonator) ×
2
Mode 1: The frequency of the external clock input from the EXTAL pin is quadrupled by PLL
circuit 2, and then the clock is supplied to this LSI. Since the input clock frequency ranging 10
MHz to 12.5 MHz can be used, the CKIO frequency ranges from 40 MHz to 50 MHz.
Rev. 4.00 Sep. 13, 2007 Page 196 of 502
REJ09B0239-0400