SH7606 Datasheet, PDF (233/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 9 Watchdog Timer (WDT)
Note: The writing method for WTCNT differs from other registers so that the WTCNT value
cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.
9.2.2 Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
counting, bits to select the timer mode and overflow flags, and enable bits.
WTCSR holds its value in the internal reset state due to the WDT overflow. WTCSR is initialized
to H'00 by a power-on reset input to the pin and an H-UDI reset. To use it for counting the clock
settling time when leaving software standby mode, WTCSR holds its value after a counter
overflow.
Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a byte access to read
WTCSR.
Note: The writing method for WTCNT differs from other registers so that the WTCNT value
cannot be changed accidentally. For details, see section 9.2.3, Notes on Register Access.
Rev. 4.00 Sep. 13, 2007 Page 207 of 502
REJ09B0239-0400