SH7606 Datasheet, PDF (109/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 6 Interrupt Controller (INTC)
6.2 Input/Output Pins
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Non-maskable interrupt input pin
Interrupt request input pins
Abbr.
NMI
IRQ0 to
IRQ7
I/O
Input
Input
Function
Input of non-maskable interrupt request
signal
Input of maskable interrupt request
signals
6.3 Register Descriptions
The interrupt controller has the following registers. For details on the addresses of these registers
and the states of these registers in each processing state, see section 18, List of Registers.
• Interrupt control register 0 (ICR0)
• IRQ control register (IRQCR)
• IRQ status register (IRQSR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
Rev. 4.00 Sep. 13, 2007 Page 83 of 502
REJ09B0239-0400