SH7606 Datasheet, PDF (211/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
This LSI
A25 to A0
D7 to D0
D15 to D8
RD/WR
CE1A
CE2A
RD
WE
ICIORD
ICIOWR
I/O Port
WAIT
IOIS16
G
G
DIR
G
DIR
G
Card
detection
circuit
PC card
(memory or I/O)
A25 to A0
D7 to D0
D15 to D8
CE1
CE2
OE
WE/PGM
IORD
IOWR
REG
WAIT
IOIS16
CD1,CD2
Figure 7.30 Example of PCMCIA Interface Connection
Basic Timing for Memory Card Interface: Figure 7.31 shows the basic timing of the PCMCIA
IC memory card interface. If areas 5 and 6 in the physical space are specified as the PCMCIA
interface, accessing the common memory areas in areas 5 and 6 automatically accesses with the IC
memory card interface. If the external bus frequency (CKIO) increases, the setup times and hold
times for the address pins (A25 to A0), card enable signals (CE1A, CE2A, CE1B, CE2B), and
write data (D15 to D0) to the RD and WE signals become insufficient. To prevent this error, this
LSI can specify the setup times and hold times for areas 5 and 6 in the physical space
independently, using CS5BWCR and CS6BWCR. In the PCMCIA interface, as in the normal
space interface, a software wait or hardware wait can be inserted using the WAIT pin. Figure 7.32
shows the PCMCIA memory bus wait timing.
Rev. 4.00 Sep. 13, 2007 Page 185 of 502
REJ09B0239-0400