SH7606 Datasheet, PDF (169/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
7.5 Operation
7.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the most significant byte (MSByte) of multiple byte data is
stored in the lower address, and little endian, in which the least significant byte (LSByte) of
multiple byte data is stored in the lower address. Endian is specified at a power-on reset by the
external pin (MD5). When pin MD5 is driven low at a power-on reset, the endian will become big
endian and when pin MD5 is driven high at a power-on reset, the endian will become little endian.
Two data bus widths (8 bits and 16 bits) are available for normal memory and byte-selection
SRAM. Only 16-bit data bus width is available for SDRAM. Two data bus widths (8 bits and 16
bits) are available for PCMCIA interface. Data alignment is performed in accordance with the data
bus width of the device and endian. This also means that when longword data is read from a byte-
width device, the read operation must be done four times. In this LSI, data alignment and
conversion of data length is performed automatically between the respective interfaces.
Tables 7.6 to 7.9 show the relationship between endian, device data width, and access unit.
Rev. 4.00 Sep. 13, 2007 Page 143 of 502
REJ09B0239-0400