SH7606 Datasheet, PDF (84/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 3 Cache
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address to be written to external memory
Longword 0 to 3: One line of cache data to be written to external memory
Figure 3.3 Write-Back Buffer Configuration
3.3.5 Coherency of Cache and External Memory
Coherency between the cache and the external memory must be ensured by software. When
memory shared by this LSI and another device is allocated to a cacheable address space, invalidate
and write back the cache by accessing the memory-mapped cache, as required.
3.4 Memory-Mapped Cache
To allow software management of the cache, cache contents can be read from or written to by the
MOV instructions. The address array is allocated to addresses H'F0000000 to H'F0FFFFFF, and
the data array to addresses H'F1000000 to H'F1FFFFFF. The address array and data array must be
accessed in longwords, and instruction fetches cannot be performed.
3.4.1 Address Array
The address array is allocated to H'F0000000 to H'F0FFFFFF. To access an address array, the 32-
bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.
In the address field, specify the entry address for selecting the entry, W for selecting the way, A
for enabling or disabling the associative operation, and H'F0 for indicating address array access.
As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates way 2, and 11 indicates way 3.
In the data field, specify the tag address, LRU bits, U bit, and V bit. Always clear the upper three
bits (bits 31 to 29) of the tag address to 0. Figure 3.4 shows the address and data formats. The
following three operations are available in the address array.
Address-Array Read: Read the tag address, LRU bits, U bit, and V bit for the entry that
corresponds to the entry address and way specified by the address field of the read instruction. In
reading, the associative operation is not performed, regardless of whether the associative bit (A
bit) specified in the address is 1 or 0.
Rev. 4.00 Sep. 13, 2007 Page 58 of 502
REJ09B0239-0400