SH7606 Datasheet, PDF (522/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Item
Figure 19.27 Synchronous DRAM Burst
Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACT + WRITE
Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle)
Page Revision (See Manual for Details)
469 Amended.
CKIO
Tr
Tc1
Tc2
Tc3
Tc4
A25 to A0
t_AD1
t_AD1
t_AD1
t_AD1
Row
address
Column
address
Column
address
t_AD1
Column
address
t_AD1
Column
address
Figure 19.28 Synchronous DRAM Burst
470 Amended.
Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command,
CKIO
Same Row Address, WTRCD = 0 Cycle,
TRWL = 0 Cycle)
A25 to A0
Tnop
Tc1
Tc2
Tc3
Tc4
tAD1
tAD1
Column
address
t_AD1
Column
address
t_AD1
Column
address
t_AD1
Column
address
Figure 19.29 Synchronous DRAM Burst
471
Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACT + WRITE
Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)
Amended.
Tp
CKIO
t_AD1
A25 to A0
Tap
Tr
Tc1
Tc2
Tc3
Tc4
Row address
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column
address
Column
address
Column
address
Column
address
Rev. 4.00 Sep. 13, 2007 Page 496 of 502
REJ09B0239-0400