SH7606 Datasheet, PDF (523/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Index
A
Access wait control................................. 152
Address array............................................ 58
Address error exception handling ............. 71
Address error sources ............................... 71
Address multiplexing.............................. 156
Addressing modes..................................... 28
Arithmetic operation instructions ............. 41
Asynchronous Mode............................... 273
Auto-refreshing....................................... 175
B
Bank active ............................................. 168
Basic timing............................................ 148
Basic timing for I/O card interface ......... 187
Basic timing for memory
card interface .......................................... 185
Bit rate .................................................... 257
Boundary scan ........................................ 413
Branch instructions ................................... 45
Burst read................................................ 163
Burst write .............................................. 167
Bus state controller (BSC) ...................... 107
Byte-selection SRAM interface .............. 180
Coherency of cache and
external memory ....................................... 58
Compare match timer (CMT) ................. 225
Control registers........................................ 21
CPU........................................................... 19
D
Data array.................................................. 59
Data register............................................ 363
Data transfer instructions .......................... 39
Divided areas and cache............................ 53
E
Endian/access size and data alignment ... 143
Exception handling ................................... 65
Exception handling operations.................. 66
Exception handling vector table................ 67
Extension of chip select (CSn)
assertion period ....................................... 153
F
Features of instructions ............................. 25
C
Cache ........................................................ 51
Cache structure ......................................... 51
Cases when exceptions are accepted......... 76
Changing clock operating mode ............. 202
Changing division ratio........................... 201
Changing frequency................................ 200
Changing multiplication ratio ................. 200
Clock operating modes ........................... 196
Clock Pulse Generator (CPG)................. 193
G
General illegal instructions ....................... 75
General registers (Rn) ............................... 21
H
Host interface (HIF)................................ 301
H-UDI Interrupt ...................................... 412
H-UDI Reset ........................................... 412
Rev. 4.00 Sep. 13, 2007 Page 497 of 502
REJ09B0239-0400