SH7606 Datasheet, PDF (332/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
Initial
Bit
Bit Name Value R/W Description
7
REG5
0
R/W* HIF Internal Register Select
6
REG4
0
5
REG3
0
4
REG2
0
3
REG1
0
2
REG0
0
R/W*
R/W*
R/W*
R/W*
R/W*
These bits specify which register among HIFGSR,
HIFSCR, HIFMCR, HIFIICR, HIFEICR, HIFADR,
HIFDATA, and HIFBCR is accessed by an external
device.
000000: HIFGSR
000001: HIFSCR
000010: HIFMCR
000011: HIFIICR
000100: HIFEICR
000101: HIFADR
000110: HIFDATA
001111: HIFBCR
Other than above: Setting prohibited
1
BYTE1 0
R/W* Internal Register Byte Specification
0
BYTE0 0
R/W*
These bits specify in advance the target word location
before the external device accesses a register among
HIFGSR, HIFSCR, HIFMCR, HIFIICR, HIFEICR,
HIFADR, HIFDATA, and HIFBCR.
• When HIFSCR.BO = 0
00:Bits 31 to 16 in register
01: Setting prohibited
10: Bits 15 to 0 in register
11: Setting prohibited
• When HIFSCR.BO = 1
00: Bits 15 to 0 in register
01: Setting prohibited
10: Bits 31 to 16 in register
11: Setting prohibited
However, when HIFDATA is selected using bits REG5 to
REG0, each time reading or writing of HIFDATA occurs,
these bits change according to the following rule.
00 → 10 → 00 → 10... repeated
Note: * This bit can be only written to by an external device while the HIFRS pin is held high. It
cannot be written to by the on-chip CPU.
Rev. 4.00 Sep. 13, 2007 Page 306 of 502
REJ09B0239-0400