SH7606 Datasheet, PDF (27/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 1 Overview
Section 1 Overview
This LSI is a CMOS single-chip microcontroller that integrates a high-speed CPU core using an
original Renesas Technology RISC (Reduced Instruction Set Computer) architecture with
supporting a variety of peripheral functions.
The CPU of this LSI has a RISC (Reduced Instruction Set Computer) type instruction set. The
CPU basically operates at a rate of one instruction per cycle, offering a great improvement in
instruction execution speed. In addition, the 32-bit internal architecture provides improved data
processing power. With this CPU, it has become possible to assemble low-cost, high-
performance/high-functionality systems even for applications such as realtime control, which
could not previously be handled by microcontrollers because of their high-speed processing
requirements.
This LSI supports peripheral functions necessary for system configuration, such as cache memory,
RAM, timers, a serial communication interface with on-chip FIFO (SCIF), host interface (HFI),
interrupt controller (INTC), and I/O ports.
The external memory access support function of this LSI enables direct connection to various
types of memory, such as standard memory, SDRAM, and PCMCIA. This greatly reduces system
cost.
1.1 Features
The features of this LSI are shown below.
CPU:
• Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer)
architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits) executed in two to
five cycles
• C language-oriented 62 basic instructions
Note: Some specifications on the slot illegal instruction differ from the conventional SH2 core.
For details, see section 5.8, Usage Notes, in section 5, Exception Handling.
Rev. 4.00 Sep. 13, 2007 Page 1 of 502
REJ09B0239-0400