SH7606 Datasheet, PDF (219/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 8 Clock Pulse Generator (CPG)
Section 8 Clock Pulse Generator (CPG)
This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The CPG consists of an oscillator, PLL circuits, and divider circuits.
8.1 Features
• Three clock modes
Selection of three clock modes depending on the frequency of a clock source and whether a
crystal resonator or external clock input is in use.
• Three clocks generated independently
An internal clock (Iφ) for the CPU and cache; a peripheral clock (Pφ) for the on-chip
peripheral modules; a bus clock (Bφ = CKIO) for the external bus interface.
• Frequency change function
Frequencies of the internal clock and peripheral clock can be changed independently using the
PLL circuit and divider circuit within the CPG. Frequencies are changed by software using the
frequency control register (FRQCR).
• Power-down mode control
The clock can be stopped in sleep mode and software standby mode and specific modules can
be stopped using the module standby function.
A block diagram of the CPG is shown in figure 8.1.
Rev. 4.00 Sep. 13, 2007 Page 193 of 502
REJ09B0239-0400