SH7606 Datasheet, PDF (259/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Peripheral operating
clock (Pφ)
Address
Section 11 Compare Match Timer (CMT)
CMCSR write cycle
T1
T2
CMCNTH
Internal write
CMCNT count-up
enable
CMCNTH
N
M
CMCNTL
X
X
Figure 11.7 Conflict between Byte-Write and Count-Up Processes of CMCNT
11.5.4 Conflict between Write Processes to CMCNT with the Counting Stopped and
CMCOR
Writing the same value to CMCNT with the counting stopped and CMCOR is prohibited. If
written, the CMF flag in CMCSR is set to 1 and CMCNT is cleared to H'0000.
Rev. 4.00 Sep. 13, 2007 Page 233 of 502
REJ09B0239-0400