SH7606 Datasheet, PDF (186/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
Table 7.13 Relationship between Register Settings and Address Multiplex Output (4)
Conditions: One 256-Mbit product (4 Mwords x 16 bits x 4 banks, 10-bit column product) is
connected with A3BSZ[1:0] = 10 (16-bit data bus width), A3ROW[1:0] = 01 (12-bit
row address), and A3COL[1:0] = 10 (10-bit column address).
Output Row
Pins of this LSI Address
Output Column
Address
Pins of SDRAM Function
A17
A27
A17
Unused
A16
A26
A16
A15
A25
A15
A14
A24*²
A24*²
A13 (BA1)
Specifies bank
A13
A23*²
A23*²
A12 (BA0)
A12
A22
A12
A11
Address
A11
A21
L/H*¹
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
Unused
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Rev. 4.00 Sep. 13, 2007 Page 160 of 502
REJ09B0239-0400