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SH7606 Datasheet, PDF (71/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series | |||
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Section 2 CPU
⢠Branch Instructions
Instruction
Operation
Code
Execution
Cycles
BF label
If T = 0, disp à 2 + PC â
PC;
if T = 1, nop
10001011dddddddd 3/1*
BF/S label
Delayed branch, if T = 0,
disp à 2 + PC â PC;
if T = 1, nop
10001111dddddddd 2/1*
BT label
If T = 1, disp à 2 + PC â
PC;
if T = 0, nop
10001001dddddddd 3/1*
BT/S label
Delayed branch, if T = 1,
disp à 2 + PC â PC;
if T = 0, nop
10001101dddddddd 2/1*
BRA label
Delayed branch,
disp à 2 + PC â PC
1010dddddddddddd 2
BRAF Rm
Delayed branch,
Rm + PC â PC
0000mmmm00100011 2
BSR label
Delayed branch, PC â PR, 1011dddddddddddd 2
disp à 2 + PC â PC
BSRF Rm
Delayed branch, PC â PR, 0000mmmm00000011 2
Rm + PC â PC
JMP @Rm
Delayed branch, Rm â PC 0100mmmm00101011 2
JSR @Rm
Delayed branch, PC â PR, 0100mmmm00001011 2
Rm â PC
RTS
Delayed branch, PR â PC 0000000000001011 2
Note: * One cycle when the branch is not executed.
T Bit
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Rev. 4.00 Sep. 13, 2007 Page 45 of 502
REJ09B0239-0400
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