SH7606 Datasheet, PDF (57/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 2 CPU
Addressing
Mode
PC relative
Immediate
Instruction
Format Effective Address Calculation Method
Rn
Effective address is sum of PC and Rn.
PC
Calculation
Formula
PC + Rn
+
PC + Rn
#imm:8
#imm:8
#imm:8
Rn
8-bit immediate data imm of TST, AND, OR, 
or XOR instruction is zero-extended.
8-bit immediate data imm of MOV, ADD, or

CMP/EQ instruction is sign-extended.
8-bit immediate data imm of TRAPA instruction 
is zero-extended and multiplied by 4.
2.4.3 Instruction Formats
This section describes the instruction formats, and the meaning of the source and destination
operands. The meaning of the operands depends on the instruction code. The following symbols
are used in the table.
xxxx: Instruction code
mmmm: Source register
nnnn: Destination register
iiii: Immediate data
dddd: Displacement
Rev. 4.00 Sep. 13, 2007 Page 31 of 502
REJ09B0239-0400