SH7606 Datasheet, PDF (97/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

5.3 Address Errors
Section 5 Exception Handling
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data is read from or written to, as shown in
table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master
Instruction CPU
fetch
Data
CPU
read/write
Bus Cycle Description
Instruction fetched from even address
Instruction fetched from odd address
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
5.3.2 Address Error Exception Source
When an address error exception is generated, the bus cycle which caused the address error ends,
the current instruction finishes, and then the address error exception handling starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value to be saved is the start address
of the instruction which caused an address error exception. When the instruction that caused
the exception is placed in the delay slot, the address of the delayed branch instruction which is
placed immediately before the delay slot.
3. The start address of the exception handling routine is fetched from the exception handling
vector table that corresponds to the generated address error, and the program starts executing
from that address. This branch is not a delayed branch.
Rev. 4.00 Sep. 13, 2007 Page 71 of 502
REJ09B0239-0400