SH7606 Datasheet, PDF (330/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
13.3 Parallel Access
13.3.1 Operation
The HIF can be accessed by combining the HIFCS, HIFRS, HIFWR, and HIFRD pins. Table 13.2
shows the correspondence between combinations of these signals and HIF operations.
Table 13.2 HIF Operations
HIFCS
HIFRS
1
×
0
0
0
0
0
1
0
1
0
×
0
×
[Legend]
×: Don't care
HIFWR
×
1
0
1
0
1
0
HIFRD
×
0
1
0
1
1
0
Operation
No operation (NOP)
Read from register specified by HIFIDX[7:0]
Write to register specified by HIFIDX[7:0]
Read from status register (HIFGSR[7:0])
Write to index register (HIFIDX[7:0])
No operation (NOP)
Setting prohibited
13.3.2 Connection Method
When connecting the HIF to an external device, a method like that shown in figure 13.2 should be
used.
External device
CS
A02
WR
RD
D15 to D00
HIF
HIFCS
HIFRS
HIFWR
HIFRD
HIFD15 to HIFD00
Figure 13.2 HIF Connection Example
Rev. 4.00 Sep. 13, 2007 Page 304 of 502
REJ09B0239-0400