SH7606 Datasheet, PDF (474/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 19 Electrical Characteristics
19.4.2 Control Signal Timing
Table 19.8 Control Signal Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.4 V to 1.6 V,
T_a = –20°C to +75°C (regular specifications),
T_a = –40°C to +85°C (wide-range specifications)
Item
Symbol Min.
Max.
Reference
Unit Figures
RES pulse width
RES setup time*¹
t
RESW
t_RESS
20*²

25

t *3
bcyc
Figures 19.7 and
ns ^19.8
RES hold time
t_RESH
15

ns
NMI setup time*¹
t
12
NMIS

ns Figure 19.8
NMI hold time
t
10
NMIH

ns
IRQ7 to IRQ0 setup time*¹
t
12
IRQS

ns
IRQ7 to IRQ0 hold time
t
10
IRQH

ns
Bus tri-state delay time 1
t_BOFF1

20
ns Figure 19.9
Bus tri-state delay time 2
t
BOFF2

20
ns
Bus buffer on time 1
t_BON1

20
ns
Bus buffer on time 2
t_BON2

20
ns
Notes: 1. The RES, NMI, and IRQ7 to IRQ0 signals are asynchronous signals. When the setup
time is satisfied, a signal change is detected at the rising edge of the clock signal. When
the setup time is not satisfied, a signal change may be delayed to the next rising edge.
2. In standby mode, t = t (10 ms). When changing the clock multiplication, t = t
RESW
OSC2
RESW
PLL1
(100 µs).
3. t_bcyc indicates the period of the external bus clock (Bφ).
CKIO
RES
t_RESS
t_RESW
t_RESS
Figure 19.7 Reset Input Timing
Rev. 4.00 Sep. 13, 2007 Page 448 of 502
REJ09B0239-0400