SH7606 Datasheet, PDF (179/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 7 Bus State Controller (BSC)
CKIO
A25 to A0
CSn
RD/WR
Read
RD
D15 to D0
Write
WEn(BEn)
D15 to D0
WAIT
BS
Wait cycles inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
Figure 7.9 Wait Cycle Timing for Normal Space Access (Wait Cycle Insertion Using WAIT)
7.5.4 Extension of Chip Select (CSn) Assertion Period
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 7.10 shows an example. A Th cycle and a Tf cycle are
added before and after a normal cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
Rev. 4.00 Sep. 13, 2007 Page 153 of 502
REJ09B0239-0400