SH7606 Datasheet, PDF (354/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 13 Host Interface (HIF)
External Device
This LSI
No. CPU
DMAC
HIF
CPU
9
Consecutive
Write data to bank 0 in
data read from
HIFRAM
bank 1 in
HIFRAM
10
Read from end → HIF bank → HIFRAM bank switching
address of bank interrupt
by HIF bank interrupt
1 in HIFRAM
occurs
handler (external device
completes and
accesses bank 0 and on-
operation halts
chip CPU accesses
bank 1)
11
Re-activate
← Assert
← Set DTRG bit to 1
DMAC
HIFDREQ
12
Consecutive
Write data to bank 1 in
data read from
HIFRAM
bank 0 in
HIFRAM
13
Read from end → HIF bank → HIFRAM bank switching
address of bank interrupt
by HIF bank interrupt
0 in HIFRAM
occurs
handler (external device
completes and
accesses bank 1 and on-
operation halts
chip CPU accesses
bank 0)
14
Re-activate
← Assert
← Set DTRG bit to 1
DMAC
HIFDREQ
Hereafter No. 12 to 14 are repeated. When a register other than HIFDATA is accessed (except
that HIFGSR read with HIFRS = low), HIFRAM consecutive read is interrupted, and No. 3 to 5
need to be done again.
Rev. 4.00 Sep. 13, 2007 Page 328 of 502
REJ09B0239-0400