SH7606 Datasheet, PDF (411/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 16 User Break Controller (UBC)
16.2.9 Break Control Register (BRCR)
BRCR sets the following conditions:
• Channels A and B are used in two independent channel conditions or under the sequential
condition.
• A break is set before or after instruction execution.
• Specify whether to include the number of execution times on channel B in comparison
conditions.
• Specify whether to include data bus on channel B in comparison conditions.
• Enable PC trace.
The break control register (BRCR) is a 32-bit readable/writable register that has break conditions
match flags and bits for setting a variety of break conditions.
Initial
Bit
Bit Name Value R/W Description
31 to 16 —
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
15
SCMFCA 0
R/W L Bus Cycle Condition Match Flag A
When the L bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1 (not
cleared
to 0). In order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel A does not
match
1: The L bus cycle condition for channel A matches
14
SCMFCB 0
R/W L Bus Cycle Condition Match Flag B
When the L bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1 (not
cleared
to 0). In order to clear this flag, write 0 into this bit.
0: The L bus cycle condition for channel B does not
match
1: The L bus cycle condition for channel B matches
Rev. 4.00 Sep. 13, 2007 Page 385 of 502
REJ09B0239-0400