SH7606 Datasheet, PDF(515/532 Page) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

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SH7606 Datasheet, PDF (515/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

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Appendix

Reset State

Power-Down Mode

Classifi-

cation Abbr.

Power-On

(HIFMD =

Low)

Power-On

(HIFMD =

High)

Software

Standby

Sleep

H-UDI Module

Standby

User

TRST

I

I

I

I

I

debugging TCK

I

I

I

I

I

interface

(H-UDI) TMS

I

I

I

I

I

TDI

I

I

I

I

I

TDO

Z

Z

ZO*6

ZO*6

Z

ASEMD

I

I

I

I

I

I/O port PA25 to PA16 Z

Z

Z

P

I/O

PB13 to PB00 Z

Z

Z

P

I/O

PC20 to PC00 Z

Z

Z

P

I/O

PD07 to PD00 Z

Z

Z

P

I/O

PE24 to PE04, Z

ï£§

Z

P

I/O

PE02 to PE00

PE03

ï£§

ï£§

Z

P

I/O

Test mode TESTMD

I

I

I

I

I

TESTOUT O

O

O

O

O

TESTOUT2

[Legend]

ï£§: This pin function is not selected as an initial state.

I:

Input

O: Output

IO: Input/output

H: High level output

L:

Low level output

Z:

High-impedance

P:

Input or output depending on the register setting

Notes: 1. Depends on the clock mode (setting of pins MD2 to MD0).

2. Depends on the HIZCNT bit in CMNCR.

3. High-impedance when HIFEBL = low

4. Depends on the HIZMEM bit in CMNCR.

5. Depends on the HIZCNT bit in CMNCR or the CKOEN bit in FRQCR.

6. This pin becomes output state only when reading data from the H-UDI and retains high-

impedance state when the pin is not output state.

Rev. 4.00 Sep. 13, 2007 Page 489 of 502

REJ09B0239-0400

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