SH7606 Datasheet, PDF (81/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 3 Cache
Initial
Bit
Bit Name Value R/W Description
0
CE
0
R/W Cache Enable
Indicates whether or not the cache function is used.
0: Cache function is not used.
1: Cache function is used.
3.2.2 Cache Control Register 3 (CCR3)
CCR3 specifies the cache size. Programs that change the contents of CCR3 should be placed in the
address space that is not cached.
Initial
Bit
Bit Name Value R/W Description
31 to 17 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
16
CSIZE2 0
R/W Cache Size
15
CSIZE1 0
R/W Writing B'100 to these bits specifies the cache size
14
CSIZE0 1
R/W ^{16 Kbytes. Write B'100 before enabling the cache by}
the CE bit in CCR1.
13 to 0 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3.3 Operation
3.3.1 Searching Cache
If the cache is enabled (the CE bit in CCR1 is set to 1), whenever an instruction or data in
H'00000000 to H'7FFFFFFF, H'8000000 to H'9FFFFFFF, and H'C0000000 to H'DFFFFFFF is
accessed, the cache will be searched to see if the desired instruction or data is in the cache. Figure
3.2 illustrates the method by which the cache is searched.
Entries are selected using bits 11 to 4 of the memory access address and the tag address of that
entry is read. The address comparison is performed on all four ways. When the comparison shows
a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not
Rev. 4.00 Sep. 13, 2007 Page 55 of 502
REJ09B0239-0400