SH7606 Datasheet, PDF (31/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

1.2 Block Diagram
Figure 1.1 is a block diagram of this LSI.
SuperH
CPU core
User break
controller
(UBC)
CPU bus (I clock)
Cache
access
controller
(CCN)
Cache
memory
16 kbytes
U memory
4 kbytes
Internal bus (B clock)
Bus state
controller
(BSC)
Peripheral
bus
controller
Section 1 Overview
External bus
Peripheral bus (P clock)
I/O port,
Pin function
controller
(PFC)
1-kbyte
SRAM
Host
interface
(HIF)
Serial
communication
interface
with FIFO
(SCIF)*1
Compare
match timer
(CMT)*2
User
debugging
interface
(H-UDI)
Interrupt
controller
(INTC)
Power-
down
mode
control
Watchdog Clock pulse
timer
generator
(WDT)
(CPG)
Notes: 1. SCIF includes three channels.
2. CMT includes two channels.
Figure 1.1 Block Diagram
Rev. 4.00 Sep. 13, 2007 Page 5 of 502
REJ09B0239-0400