SH7606 Datasheet, PDF (85/532 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH™ RISC engine Family / SH7606 Series

Section 3 Cache
Address-Array Write (Non-Associative Operation): Write the tag address, LRU bits, U bit, and
V bit, specified by the data field of the write instruction, to the entry that corresponds to the entry
address and way as specified by the address field of the write instruction. Ensure that the
associative bit (A bit) in the address field is set to 0. When writing to a cache line for which the U
bit = 1 and the V bit =1, write the contents of the cache line back to memory, then write the tag
address, LRU bits, U bit, and V bit specified by the data field of the write instruction. When 0 is
written to the V bit, 0 must also be written to the U bit for that entry.
Address-Array Write (Associative Operation): When writing with the associative bit (A bit) of
the address field set to 1, the addresses in the four ways for the entry specified by the address field
of the write instruction are compared with the tag address that is specified by the data field of the
write instruction. Write the U bit and the V bit specified by the data field of the write instruction to
the entry of the way that has a hit. However, the tag address and LRU bits remain unchanged.
When there is no way that has a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache. When the U bit of the entry that has had a hit is 1
at this time, writing back should be performed. However, when 0 is written to the V bit, 0 must
also be written to the U bit of that entry.
3.4.2 Data Array
The data array is allocated to H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry, L for indicating the longword
position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array
access. As for L, 00 indicates longword 0, 01 indicates longword 1, 10 indicates longword 2,
and 11 indicates longword 3. As for W, 00 indicates way 0, 01 indicates way 1, 10 indicates
way 2, and 11 indicates way 3.
Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be
set to 00.
Figure 3.4 shows the address and data formats.
The following two operations on the data array are available. The information in the address array
is not affected by these operations.
Data-Array Read: Read the data specified by L of the address field, from the entry that
corresponds to the entry address and the way that is specified by the address field.
Rev. 4.00 Sep. 13, 2007 Page 59 of 502
REJ09B0239-0400